CMOS Eight-Transistor Memory Cell forLow-Power High-speed Embedded SRAM

Abstract

With Migration towards low supply voltages in low-noise embedded SRAM designs, low-power, high-speed, and small physical cell area become more essential in VLSI devices. This necessitates sharing of power supplies and substrates with sensitive digital and analogue circuitry, which have large impacts on timing and power specifications of SRAMâ??s performance. A CMOS eight-transistor (8T) memory cell circuit for single and multi-port SRAM is proposed. The cell is based on the traditional cross-coupled inver